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5 V, 12-Bit nanoDAC, Serial Interface in MSOP and LFCSP Packages AD5626
FEATURES
8-lead MSOP and 8-lead LFCSP packages Complete voltage output with internal reference 1 mV/bit with 4.095 V full scale 5 V single-supply operation No external components required 3-wire serial interface, 20 MHz data loading rate Low power: 2.5 mW
GENERAL DESCRIPTION
The AD5626, a member of the nanoDAC(R) family, is a complete serial input, 12-bit, voltage output digital-to-analog converter (DAC) designed to operate from a single 5 V supply. It contains the DAC, input shift register and latches, reference, and a railto-rail output amplifier. The AD5626 monolithic DAC offers the user low cost and ease of use in 5 V only systems. Coding for the AD5626 is natural binary with the MSB loaded first. The output op amp can swing to either rail and is set to a range of 0 V to 4.095 V for a one-millivolt-per-bit resolution. It is capable of sinking and sourcing 5 mA. An on-chip reference is laser trimmed to provide an accurate full-scale output voltage of 4.095 V. This part features a serial interface that is high speed, threewire, DSP compatible with data in (SDIN), clock (SCLK), and load strobe (LDAC). There is also a chip-select pin for connecting multiple DACs. The CLR input sets the output to zero scale at power on or upon user demand. The AD5626 is specified over the extended industrial temperature range (-40C to +85C). The AD5626 is available in MSOP and LFCSP surface-mount packages.
APPLICATIONS
Portable instrumentation Digitally controlled calibration Servo controls Process control equipment PC peripherals
FUNCTIONAL BLOCK DIAGRAM
VDD
AD5626
REF
LDAC CLR
DAC REGISTER
12-BIT DAC
OUTPUT BUFFER
VOUT
INPUT REGISTER
06757-001
CS
SCLK SDIN
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
AD5626 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics ............................................................. 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 10 DAC Section ................................................................................ 10 Amplifier Section........................................................................ 10 Output Section ............................................................................ 10 Power Supply............................................................................... 10 Timing and Control ................................................................... 11 Applications Information.............................................................. 12 Power Supplies, Bypassing, and Grounding ........................... 12 Unipolar Output Operation ...................................................... 12 Operating the AD5626 on 12 V or 15 V Supplies Only ........ 13 Measuring Offset Error ............................................................. 13 Bipolar Output Operation ......................................................... 13 Generating a Negative Supply Voltage .................................... 15 A Single-Supply, Programmable Current Source................... 15 Galvanically-Isolated Interface ................................................. 15 Microprocessor Interfacing ....................................................... 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17
REVISION HISTORY
12/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD5626 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VDD = 5.0 V 5%, -40C TA +85C, B grade device, unless otherwise noted. Table 1.
Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Voltage Full-Scale Tempco 2, 3 ANALOG OUTPUT Output Current Load Regulation at Midscale Capacitive Load LOGIC INPUTS Logic Input Low Voltage High Voltage Input Leakage Current Input Capacitance AC CHARACTERISTICS2 Voltage Output Settling Time DAC Glitch Digital Feedthrough SUPPLY CHARACTERISTICS Positive Supply Current Power Dissipation Power Supply Sensitivity
1 2 3
Symbol N INL DNL VZSE VFS TCVFS IOUT LREG CL
Condition
Min 12 -1 -1 4.063
Typ
Max
Unit Bits LSB LSB LSB V ppm/C mA LSB pF
No missing codes Data = 0x000 Data = 0xFFF 1
1/4 3/4 1/2 4.095 32 7 1 500
+1 +1 3 4.111
Data = 0x800 RL = 402 to , data = 0x800 No oscillation2
5
3
VIL VIH IIL CIL tS To 1 LSB of final value3
0.8 2.4 10 10 16 15 15 1.5 0.5 7.5 2.5 0.002 2.5 1 12.5 5 0.004
V V A pF s nV-s nV-s mA mA mW mW %/%
IDD PDISS PSS
VIH = 2.4 V, VIL = 0.8 V, no load VDD = 5 V, VIL = 0 V, no load VIH = 2.4 V, VIL = 0.8 V, no load VDD = 5 V, VIL = 0 V, no load VDD = 5%
Includes internal voltage reference error. These parameters are guaranteed by design and not subject to production testing. The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region.
Rev. 0 | Page 3 of 20
AD5626
TIMING CHARACTERISTICS
@ VDD = 5.0 V 5%, -40C TA +85C, unless otherwise noted. Table 2.
Parameter 1, 2 tCH tCL tLDW tDS tDH tCLRW tLD1 tLD2 tCSS tCSH
1 2
Limit at TMIN, TMAX 30 30 20 15 15 30 15 10 30 20
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Description Clock width high Clock width low Load pulse width Data setup Data hold Clear pulse width Load setup Load hold Select Deselect
These parameters are guaranteed by design and not subject to production testing. All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Timing Diagram
SDIN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO
SCLK
tCSS
CS
tCSH
tLD1
LDAC
tLD2
SDIN
tDS
SCLK
tDH tCH tLDW tCLRW
tCL
LDAC
CLR FS ZS
tS
1 LSB ERROR BAND
tS
Figure 2. Timing Diagram
Rev. 0 | Page 4 of 20
06757-002
VOUT
AD5626 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VDD to GND Logic Inputs to GND VOUT to GND IOUT Short Circuit to GND Package Power Dissipation Thermal Resistance (JA) 8-Lead MSOP 8-Lead LFCSP Maximum Junction Temperature (TJ max) Operating Temperature Range Storage Temperature Range Lead Temperature Soldering Rating -0.3 V to +10 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V 50 mA (TJ max - TA)/JA 220C/W 62C/W 150C -40C to +85C -65C to +150C JEDEC industry standard J-STD-020
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 20
AD5626 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD 1
8
VOUT GND CLR LDAC
06757-004
VDD 1 CS 2 SCLK 3
8
VOUT GND
CS 2 SCLK 3
06757-003
AD5626
TOP VIEW (Not to Scale)
7 6 5
AD5626
7
TOP VIEW 6 CLR (Not to Scale) SDIN 4 5 LDAC
SDIN 4
Figure 3. 8-Lead MSOP Pin Configuration
Figure 4. 8-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD CS SCLK SDIN LDAC CLR GND VOUT Description Positive Supply. Nominal value 5 V 5%. Chip Select. Active low input. Clock Input. Clock input for the internal serial input shift register. Serial Data Input. Data on this pin is clocked into the internal serial register on positive clock edges of the SCLK pin. The most significant bit (MSB) is loaded first. Serial Register Data Write to DAC Register. Active low input that writes the serial register data into the DAC register. Asynchronous input. Clear DAC Register. Active low digital input that clears the DAC register to zero, setting the DAC to minimum scale. Asynchronous input. Ground. Analog ground for the DAC. This also serves as the digital logic ground reference voltage. Voltage Output from the DAC. Fixed output voltage range of 0 V to 4.095 V with 1 mV/LSB. An internal temperature stabilized reference maintains a fixed full-scale voltage independent of time, temperature, and power supply variations.
Table 5. Control Logic Truth Table1
CS2, 3 H L L L + H H H H
1 2
CLK2 X L H + L X X X X
CLR H H H H H H H L +
LD4 H H H H H - L X H
Serial Shift Register Function No effect No effect No effect Shift-register-data advanced one bit Shift-register-data advanced one bit No effect No effect No effect No effect
DAC Register Function Latched Latched Latched Latched Latched Updated with current shift register contents Transparent Loaded with all zeros Latched all zeros
+ indicates a positive logic transition; - indicates a negative logic transition; X = don't care. CS and CLK are interchangeable. 3 Returning CS high avoids an additional false clock of serial data input. 4 Do not clock in serial data while LD is low.
Rev. 0 | Page 6 of 20
AD5626 TYPICAL PERFORMANCE CHARACTERISTICS
5 VDD = 5V TA = 25C 4
OUTPUT VOLTAGE (V)
RL TIED TO AGND DATA = 0xFFF 3
1
2
1
0 10
06757-005
100
1k LOAD RESISTANCE ()
10k
100k
CH1 5.00V
CH2 100mV
M2.00ms
A CH1
210V
Figure 5. Output Voltage vs. Load
100
OUTPUT PULL-DOWN VOLTAGE (mV)
Figure 8. Broadband Noise
1.2 1.1 1.0
SUPPLY CURRENT (mA)
10
+85C +25C -40C
1
0.9 0.8 0.7 0.6 0.5 0.4
0.1
0.01
0.001
06757-006
06757-008
RL TIED TO 5V DATA = 0x000
0.3 0.2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.0001
1
10
100
1000
OUTPUT SINK CURRENT (A)
LOGIC VOLTAGE VALUE (V)
Figure 6. Output Pull-Down Voltage vs. Output Sink Current Capability
80 60
OUTPUT CURRENT (mA)
Figure 9. Supply Current vs. Logic Input Voltage
80 70
POWER SUPPLY REJECTION (dB)
60 50 40 30 20 10
06757-010
40 20 0 -20 -40 -60
06757-007
0 -10 10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
100
1k FREQUENCY (Hz)
10k
100k
OUTPUT VOLTAGE (V)
Figure 7. Short-Circuit Current
Figure 10. Power Supply Rejection vs. Frequency
Rev. 0 | Page 7 of 20
06757-009
AD5626
5.0 VFS 1 LSB DATA = 0xFFF TA = 25C
1
4.8
LDAC
VDD MIN (V)
4.6
4.4
PROPER OPERATION WHEN VDD SUPPLY VOLTAGE IS ABOVE CURVE
06757-011
OUTPUT
2
4.0 0.01
0.1
1
10
OUTPUT LOAD CURRENT (mA)
SOURCE VERTICLE SCALE OFFSET HORIZONTAL SCALE POSITION CH1 2.00V/DIV -1.95V 5.0s/DIV 22.725s CH2 200mV/DIV 3.9875mV 5.0s/DIV 22.725s
Figure 11. Minimum Supply Voltage vs. Load
Figure 14. Rise Time Detail
2.11 2.10 2.09
0x7FF 0x800
0x800 0x7FF
LDAC
1
2.08
VOUT (V)
2.07 2.06 2.05
06757-012
OUTPUT
2
2.04 2.03
0
0.5
1.0
1.5
2.0 TIME (ns)
2.5
3.0
3.5
4.0
SOURCE VERTICLE SCALE OFFSET HORIZONTAL SCALE POSITION CH1 2.00V/DIV -1.95V 5.0s/DIV 22.725s CH2 200mV/DIV 87.6mV 5.0s/DIV 22.725s
Figure 12. Midscale DAC Glitch Performance
Figure 15. Fall Time Detail
0.20 0.15 0.10
INL (LSB)
+85C +25C -40C
0.05 0
-0.05
OUTPUT 2
06757-013
VDD = 5V -0.15 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
SOURCE VERTICLE SCALE OFFSET HORIZONTAL SCALE POSITION CH2 1.00V/DIV 2.90V 50.0s/DIV 105.758s
Figure 13. Large Signal Settling Time
Figure 16. Integral Linearity Error vs. Digital Code
Rev. 0 | Page 8 of 20
06757-016
-0.10
06757-015
06757-014
4.2
AD5626
60 TUE = INL + ZS + FS SS = 300 UNITS TA = 25C
10 VDD = 5V NO LOAD DATA = 0xFFF 1
40
30
OUTPUT NOISE DENSITY (V/Hz)
06757-017
50
NNUMBER OF UNITS
20
0.1
10
0 -12
-8
-4
0
4
8
12
0.01 10
100
1k FREQUENCY (Hz)
10k
100k
TOTAL UNADJUSTED ERROR (mV)
Figure 17. Total Unadjusted Error Histogram
4.115 4.110 VDD = 5V NO LOAD SS = 300 UNITS AVG + 3 5 4
Figure 20. Output Voltage Noise vs. Frequency
135 UNITS TESTED
OUTPUT VOLTAGE CHANGE (mV)
3 2 1 0 -1 -2 -3 -4 -5 0
06757-021
FULL-SCALE OUTPUT (V)
4.105 4.100 4.095 4.090 4.085 4.080 4.075 -50 AVG
AVERAGE
AVG - 3
06757-018
READINGS NORMALIZED TO ZERO HOUR TIME POINT 200 400 600 800 1000
-25
0
25
50
75
100
125
RANGE
1200
TEMPERATURE (C)
HOURS OF OPERATION AT 125C
Figure 18. Full-Scale Output Voltage vs. Temperature
0.50 0.45 0.40 1.6 1.4 1.2 1.0 0.8 0.6 0.4
Figure 21. Long-Term Drift Accelerated by Burn-In
VDD = 4.75V VDD = 5V VDD = 5.25V
ZERO SCALE (mV)
0.35 0.30 0.25 0.20 0.15 0.10
06757-019
SUPPLY CURRENT (mA)
0.05 0 -40 -20 0 20 40 60 80
0 -40
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 19. Zero-Scale Voltage vs. Temperature
Figure 22. Supply Current vs. Temperature
Rev. 0 | Page 9 of 20
06757-022
0.2
06757-020
AD5626 THEORY OF OPERATION
The AD5626 is a complete, ready-to-use, 12-bit digital-to-analog converter (DAC). It contains a voltage-switched, 12-bit, lasertrimmed DAC, a curvature-corrected band gap reference, a rail-to-rail output op amp, a DAC register, and a serial data input register. The serial data interface consists of an SCLK, serial data in (SDIN), and a load strobe (LDAC). This basic 3-wire interface offers maximum flexibility for interface to the widest variety of serial data input loading requirements. In addition, a CS select is provided for multiple packaging loading and a power-on-reset CLR pin to simplify start or periodic resets.
VDD P-CH
VOUT N-CH
AGND
Figure 24. Equivalent Analog Output Circuit
DAC SECTION
The DAC is a 12-bit voltage mode device with an output that swings from the GND potential to the 2.5 V internal band gap voltage. It uses a laser trimmed, rail-to-rail ladder which is switched by N-channel MOSFETs. The output voltage of the DAC has a constant resistance independent of digital input code. The DAC output internally connects to the rail-to-rail output op amp.
AMPLIFIER SECTION
A low power consumption, precision amplifier buffers the DAC output. This amplifier contains a differential PNP pair input stage that provides low offset voltage and low noise, as well as the ability to amplify the zero-scale DAC output voltages. The rail-to-rail amplifier is configured with a gain of 1.6384 (= 4.095 V/2.5 V) to set the 4.095 V full-scale output (1 mV/LSB). See Figure 23 for an equivalent circuit schematic of the analog section.
VOLTAGE SWITCHED 12-BIT RAIL-TO-RAIL CONVERTER BAND GAP REFERENCE 2R RAIL-TO-RAIL OUTPUT AMPLIFIER
Figure 24 shows an equivalent output schematic of the rail-torail amplifier with its N-channel pull-down FETs that pull an output load directly to GND. The output sourcing current is provided by a P-channel pull-up device that can supply GND terminated loads, especially at the low supply tolerance values of 4.75 V. Figure 5 and Figure 6 provide information on output swing performance near ground and full-scale as a function of load. In addition to resistive load driving capability, the amplifier has also been carefully designed and characterized for up to 500 pF capacitive load driving capability.
POWER SUPPLY
The very low power consumption of the AD5626 is a direct result of a circuit design optimizing use of the CBCMOS process. By using the low power characteristics of the CMOS for the logic, and the low noise, tight matching of the complementary bipolar transistors, good analog accuracy is achieved. For power consumption sensitive applications, it is important to note that the internal power consumption of the AD5626 is strongly dependent on the actual logic input voltage levels present on the SDIN, CS, LDAC, and CLR pins. Because these inputs are standard CMOS logic structures, they contribute static power dissipation dependent on the actual driving Logic VOH and Logic VOL voltage levels. The graph in Figure 9 shows the effect on total AD5626 supply current as a function of the actual value of input logic voltage. Consequently, use of CMOS logic vs. TTL minimizes power dissipation in the static state. A VIL = 0 V on the SDIN, CS, and CLR pins provides the lowest standby power dissipation of 2.5 mW (500 A x 5 V). As with any analog system, it is recommended that the AD5626 power supply be bypassed on the same PC card that contains the chip. Figure 10 shows the power supply rejection vs. frequency performance. This should be taken into account when using higher frequency, switched mode power supplies with ripple frequencies of 100 kHz and higher. One advantage of the rail-to-rail output amplifier used in the AD5626 is the wide range of usable supply voltage. The part is fully specified and tested over temperature for operation from 4.75 V to 5.25 V. If reduced linearity and source current capability near full scale can be tolerated, operation of the AD5626 is possible down to 4.3 V. The minimum operating supply
BUFFER
R 2R R1 R2
VOUT
2.5V
R 2R AV = 1.638 (= 4.095V/2.5V)
Figure 23. Equivalent AD5626 Schematic of Analog Section
The op amp has a 16 s typical settling time to 0.01%. There are slight differences in settling time for negative slewing signals vs. positive slewing signals. See the oscilloscope photos in the Typical Performance Characteristics section of this data sheet.
OUTPUT SECTION
The rail-to-rail output stage of this amplifier is designed to provide precision performance when operating near either power supply.
06757-023
SPDT N-CHANNEL FET SWITCHES
2R 2R
Rev. 0 | Page 10 of 20
06757-024
AD5626
voltage vs. load current plot, shown in Figure 11, provides information for operation below VDD = 4.75 V. register by strobing the LDAC pin. The DAC register uses a level sensitive LDAC strobe that should be returned high before any new data is loaded into the serial input register. At any time, the contents of the DAC register can be reset to zero by strobing the CLR pin that causes the DAC output voltage to go to zero volts. Figure 2 details all of the timing requirements together with Table 5, the control logic truth table.
TIMING AND CONTROL
The AD5626 has a separate serial input register from the 12-bit DAC register that allows preloading of a new data value into the serial register without disturbing the present DAC output voltage. After the new value is fully loaded in the serial input register, it can be asynchronously transferred to the DAC
Rev. 0 | Page 11 of 20
AD5626 APPLICATIONS INFORMATION
POWER SUPPLIES, BYPASSING, AND GROUNDING
All precision converter products require careful application of good grounding practices to maintain full rated performance. Because the AD5626 has been designed for 5 V applications, it is ideal for those applications under microprocessor or microcomputer control. In these applications, digital noise is prevalent; therefore, special care must be taken to ensure that its inherent precision is maintained by exercising particularly good engineering judgment when addressing the power supply, grounding, and bypassing issues using the AD5626. Use a well-filtered and regulated power supply for the AD5626. The device has been completely characterized for a 5 V supply with a tolerance of 5%. Because a 5 V logic supply is almost universally available, it is not recommended to connect the DAC directly to an unfiltered logic supply without careful filtering. Tapping a logic circuit supply for the DAC supply is unwise because fast logic with nanosecond transition edges induce high current pulses. The high transient current pulses can generate glitches hundreds of millivolts in amplitude due to wiring resistances and inductances. This high frequency noise corrupts the analog circuits internal to the DAC and causes errors. Even though their spike noise is lower in amplitude, directly tapping the output of a 5 V system supply can cause errors because these supplies are of the switching regulator type that can and do generate a great deal of high frequency noise. Therefore, power the DAC and any associated analog circuitry directly from the system power supply outputs using appropriate filtering. Figure 25 illustrates how a clean, analog-grade supply can be generated from a 5 V logic supply using a differential LC filter with separate power supply and return lines. With the values shown, this filter can easily handle 100 mA of load current without saturating the ferrite cores. Higher current capacity can be achieved with larger ferrite cores. For lowest noise, all electrolytic capacitors should be of the low equivalent series resistance (ESR) type.
TTL/CMOS LOGIC CIRCUITS FERRITE BEADS: 2 TURNS +5V + 100F ELECT. + 10-20F TANT. 0.1F CER. +5V RETURN 5V POWER SUPPLY
06757-025
for the internal voltage reference and the output amplifier. Therefore, to minimize errors, connect the ground connection of the AD5626 to a high quality analog ground, such as the one previously described. Generous bypassing of the DACs supply effectively reduces supply line induced errors. Local supply bypassing consisting of a 10 F tantalum electrolytic capacitor in parallel with a 0.1 F ceramic capacitor is recommended. Connect the decoupling capacitors between the DAC supply pin (Pin 1) and the analog ground (Pin 7). Figure 26 shows how the ground and bypass connections should be made to the AD5626.
5V
1
CS CLR LDAC SCLK SDIN
2 6 5 3 4
VDD
+
10F
0.1F
AD5626
VOUT 8 VOUT
GND
7
06757-026
TO ANALOG GROUND
Figure 26. Recommended Grounding and Bypassing Scheme for the AD5626
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD5626. As shown in Figure 27, the AD5626 is designed to drive loads as low as 2 k in parallel with 500 pF. The code table for this operation is provided in Table 6.
5V 0.1F
1
10F +
CS CLR LDAC SCLK SDIN
2 6 5 3 4
VDD
AD5626
VOUT 8 2k GND
0V VOUT 4.095V 500pF
Figure 27. Unipolar Output Operation
Table 6. Unipolar Code Table
Hexadecimal Number in DAC Register FFF 801 800 7FF 000 Decimal Number in DAC Register 4095 2049 2048 2047 0 Analog Output Voltage (V) 4.095 2.049 2.048 2.047 0
Figure 25. Properly Filtering a 5 V Logic Supply Yields a High Quality Analog Supply
To fit the AD5626 in an 8-lead package, only one ground connection to the device is accommodated. The ground connection of the DAC serves as the return path for supply currents as well as the reference point for the digital input thresholds. The ground connection also serves as the supply rail
Rev. 0 | Page 12 of 20
06757-027
7
AD5626
OPERATING THE AD5626 ON 12 V OR 15 V SUPPLIES ONLY
Although the AD5626 has been specified to operate on a single, 5 V supply, a single 5 V supply may not be available in many applications. Because the AD5626 consumes no more than 2.5 mA maximum, an integrated voltage reference, such as the ADR02, can be used as the 5 V supply for the AD5626. See Figure 28 for the circuit configuration. Notice that the output voltage of the reference requires no trimming because of the excellent load regulation and tight initial output voltage tolerance of the ADR02. Although the maximum supply current of the AD5626 is 2.5 mA, local bypassing of the ADR02 output with at least 0.1 F at the DAC voltage supply pin is recommended to prevent the internal digital circuits of the DAC from affecting the internal voltage reference of the DAC.
12V OR 15V 1F
specified to be 3 LSBs. Because zero scale coincides with zero volt, it is not possible to measure negative offset error.
5V 0.1F
1
CS CLR LDAC SCLK SDIN
2 6 5 3 4
VDD
AD5626
VOUT 8 R GND
7
VOUT 200A, MAX
V-
SET CODE = 0x000 AND MEASURE V OUT
Figure 29. Measuring Zero-Scale or Offset Error
2
ADR02
4
6
0.1F
1
CS CLR LDAC SCLK SDIN
2 6 5 3 4
VDD
By adding a pull-down resistor from the output of the AD5626 to a negative supply as shown in Figure 29, offset errors can be read at zero code. This configuration forces the output P-channel MOSFET to source current to the negative supply thereby allowing the designer to determine in which direction the offset error appears. The value of the resistor should be such that, at zero code, current through the resistor is 200 A, maximum.
AD5626
8
BIPOLAR OUTPUT OPERATION
VOUT
GND
06757-028
7
Although the AD5626 has been designed for single-supply operation, bipolar operation is achievable using the circuit illustrated in Figure 30. The circuit uses a single-supply, railto-rail OP295 op amp and the REF03 to generate the -2.5 V reference required to level shift the DAC output voltage. Note that the -2.5 V reference is generated without the use of precision resistors. The circuit configuration provides an output voltage in the range of -5 V VOUT +5 V and is coded in complementary offset binary. Although each DAC LSB corresponds to 1 mV, each output LSB has been scaled to 2.44 mV. Table 7 lists the relationship between the digital codes and output voltage. The transfer function of the circuit is given by
VO = -1 mV x Digital Code x R4 R4 + 2.5 x R1 R2
Figure 28. Operating the AD5626 on 12 V or 15 V Supplies Using an ADR02 Voltage Reference
MEASURING OFFSET ERROR
One of the most commonly specified endpoint errors associated with real world nonideal DACs is offset error. In most DAC testing, the offset error is measured by applying the zero-scale code and measuring the output deviation from 0 V. There are some DACs where offset errors are present but not observable at the zero scale because of other circuit limitations (for example, zero coinciding with single-supply ground). In these DACs, nonzero output at zero code cannot be read as the offset error. In the AD5626, for example, the zero-scale error is
and, for the circuit values shown, becomes VO = -2.44 mV x Digital Code + 5 V
Rev. 0 | Page 13 of 20
06757-029
AD5626
+5V 0.1F 10F FULL-SCALE ADJUST R4 23.7k
1
+
VDD
CS CLR LDAC SCLK SDIN
2 6 5 3 4
+5V R1 10k
6
P3 500
AD5626
VOUT 8
- A2
8 7 4
R2 12.7k GND
7
R3 247k
5
+
-5V VO +5V
-2.5V +5V 0.1F
2 6
P2 10k
-5V ZERO-SCALE ADJUST
0.01F 2.5V TRIM
100
2
- A1
1
ADR03
5 4
P1 10k
-2.5V
3
+
06757-030
A1, A2 = 1/2 OP295
Figure 30. Bipolar Output Operation
+5V 0.1F
2
ADR03
4
R1
6
R2
+2.5V +5V 0.1F
2 1
+5V - A1
3 8 1 4
VO
CS CLR LDAC SCLK SDIN
2 6 5 3 4
VDD
+
AD5626
VOUT 8
R3 R4
-5V
A1 = 1/2 OP295 GND
7
VOUTRANGE 2.5V 5V
R1 10k 10k
R2
R3
R4
06757-031
10k 10k
15k + 274
20k 10k 43.2k + 499
Figure 31. Bipolar Output Operation Without Trim
Table 7. Bipolar Code
Hexadecimal Number in DAC Register FFF 801 800 7FF 000 Decimal Number in DAC Register 4095 2049 2048 2047 0 Analog Output Voltage (V) -4.9976 -2.44E - 3 0 +2.44E - 3 +5
matching. Mismatching between R1 and R2 causes offset and gain errors whereas an R4 to R1 or R4 to R2 mismatch yields gain errors. For applications that do not require high accuracy, the circuit illustrated in Figure 31 can also be used to generate a bipolar output voltage. In this circuit, only one op amp is used and no potentiometers are used for offset and gain trim. The output voltage is coded in offset binary and is given by
R2 R4 R2 VO = 1 mV x Digital Code x x 1 + - 2.5 x R1 R1 R3 + R4
To maintain monotonicity and accuracy, R1, R2, and R4 should be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient
Rev. 0 | Page 14 of 20
AD5626
For the 2.5 V output range and the circuit values shown in the table in Figure 31, the transfer equation becomes VO = 1.22 mV x Digital Code - 2.5 V Similarly, for the 5 V output range, the transfer equation becomes VO = 2.44 mV x Digital Code - 5 V
CS CLR LDAC SCLK SDIN
2 6 5 3 4 2
5V 0.1F
1
VS LOAD
VDD
AD5626
VOUT 8
3
+5V +
A1
- GND
7
1
2N2222
GENERATING A NEGATIVE SUPPLY VOLTAGE
Some applications may require bipolar output configuration but only have a single power supply rail available. This is very common in data acquisition systems using microprocessorbased systems. In these systems, only 12 V, 15 V, and/or 5 V are available. Figure 32 shows a method for generating a negative supply voltage using one CD4049, a CMOS hexadecimal inverter, and operating on 12 V or 15 V. The circuit is essentially a charge pump where two of the six inverters are used as an oscillator. For the values shown, the frequency of oscillation is approximately 3.5 kHz and is fairly insensitive to supply voltage because R1 > 2 x R2. The remaining four inverters are wired in parallel for higher output current. The square wave output is level translated by C2 to a negative-going signal rectified using a pair of 1N4001s, and then filtered by C3. With the values shown, the charge pump provides an output voltage of -5 V for currents loading in the range 0.5 mA IOUT 10 mA with a 15 V supply and 0.5 mA IOUT 7 mA with a 12 V supply.
7 INVERTERS = CD4049 9 3 R1 510k 2 5 R2 5.1k C1 0.02F 4 11 14 12 15 D1 1N4001 C3 47F 10 C2 47F + D2 1N4001 R3 470 -5V
06757-032
A1 = 1/2 OP295
R1 4.02k P1 200 FULL-SCALE ADJUST
Figure 33. A Single-Supply, Programmable Current Source
The usable output voltage range of the current sink is 5 V to 60 V. The low limit of the range is controlled by transistor saturation, and the high limit is controlled by the collector-base breakdown voltage of the 2N2222.
GALVANICALLY-ISOLATED INTERFACE
In many process control type applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. An iCoupler(R) can provide isolation in excess of 2.5 kV. The serial loading structure of the AD5626 makes it ideal for isolated interfaces as the number of interface lines is kept to a minimum. Figure 34 illustrates a 4-channel isolated interface using an ADuM1400. For further information, visit http://www.analog.com/icouplers.
MICROCONTROLLER SERIAL CLOCK OUT SERIAL DATA OUT SYNC OUT CONTROL OUT
V IA
6
ADuM1400*
ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE
V OA V OB V OC V OD
1N5231 5.1V ZENER
TO SCLK TO SDIN TO SYNC TO LDAC
06757-034
+
V IB V IC V ID
Figure 32. Generating a -5 V Supply When Only 12 V or 15 V Is Available
A SINGLE-SUPPLY, PROGRAMMABLE CURRENT SOURCE
The circuit in Figure 33 shows how the AD5626 can be used with an OP295 single-supply, rail-to-rail, output op amp to provide a digitally programmable current sink from VSOURCE that consumes less than 3.8 mA, maximum. The DAC output voltage is applied across R1 by placing the 2N2222 transistor in the feedback loop of the OP295. For the circuit values shown, the full-scale output current is 1 mA, which is given by the following equation:
I OUT = DW x 4.095V R1
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 34. An iCoupler-Isolated DAC Interface
where DW = the binary digital input code of the AD5626.
Rev. 0 | Page 15 of 20
06757-033
AD5626
MICROPROCESSOR INTERFACING
AD5626 to MC68HC11 Interface
The circuit illustrated in Figure 35 shows a serial interface between the AD5626 and the MC68HC11 8-bit microcontroller. SCK of the MC68HC11 drives SCLK of the AD5626, whereas the MOSI output drives the serial data line, SDIN, of the AD5626. The CLR, LDAC, and CS signals of the DAC are derived from the PC1, PD5, and PC0 port lines, respectively, as shown. For correct operation of the serial interface, configure the MC68HC11 such that its CPOL bit is set to 1 and its CPHA bit is also set to 1. When the serial data is to be transmitted to the DAC, PC0 is taken low, asserting the CS input of the DAC. When the MC68HC11 is configured in this manner, serial data on MOSI is valid on the rising edge of SCLK. The MC68HC11 transmits its serial data in 8-bit bytes (MSB first), with only eight rising clock edges occurring in the transmit cycle. To load data to the input serial register of the AD5626, PC0 is left low after the first eight bits are transferred, and a second byte of data is then transferred serially to the AD5626. During the second byte load, the first 4 MSBs of the first byte are pushed out of the input shift register of the DAC. At the end of the second byte load, PC0 is taken high. To prevent accidental advancing of the internal shift register, SCLK must already be asserted before PC0 is taken high. To transfer the contents of the input shift register to the DAC register, PD5 is taken low, asserting the LDAC input. The CLR input of the DAC, controlled by the MC68HC11 PC1 port, provides an asynchronous clear function, setting the DAC output to zero.
MC68HC11*
PC1 PC0 PD5 SCK MOSI
AD5626
CLR CS LDAC SCLK
06757-035
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 35. AD5626 to MC68HC11 Interface
Rev. 0 | Page 16 of 20
AD5626 OUTLINE DIMENSIONS
3.20 3.00 2.80
3.20 3.00 2.80
8
5
1
5.15 4.90 4.65
4
PIN 1 0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8 0 0.80 0.60 0.40
0.23 0.08
COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 36. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
3.00 BSC SQ 0.30 0.23 0.18
5 8 EXPOSED PAD (BOTTOM VIEW)
0.65 BSC
PIN 1 INDEX AREA 0.50 0.40 0.30
TOP VIEW
1.74 1.64 1.49
4
1
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 NOM
2.48 2.38 2.23 0.05 MAX 0.02 NOM
PIN 1 INDICATOR (R 0.19)
Figure 37. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-8-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5626BRMZ1 AD5626BRMZ-REEL71 AD5626BCPZ1 AD5626BCPZ-REEL71
1
INL (LSB) 1 1 1 1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead MSOP 8-Lead MSOP 8-Lead LFCSP_WD 8-Lead LFCSP_WD
Package Option RM-8 RM-8 CP-8-3 CP-8-3
062507-A
0.20 REF
Branding DAP DAP DAP DAP
Z = RoHS Compliant Part.
Rev. 0 | Page 17 of 20
AD5626 NOTES
Rev. 0 | Page 18 of 20
AD5626 NOTES
Rev. 0 | Page 19 of 20
AD5626 NOTES
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06757-0-12/07(0)
Rev. 0 | Page 20 of 20

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